Phase-locked loops (PLLs) are used in many communication systems. A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. A phase-locked loop may be used to maintain timing integrity and clock synchronization. Ring oscillator-type, voltage-controlled oscillators (VCOs) have been used in phase-locked loop systems for high-speed clock generation. An advantage of a ring oscillator-type voltage-controlled oscillator is that it may be integrated in complementary metal oxide semiconductor (CMOS) technology without introducing additional process and modeling complexity. On the other hand, disadvantages of a ring oscillator-type, voltage-controlled oscillator include jitter due to higher thermal noise and power supply noise. Also, as complementary metal oxide semiconductor process technology scales down in size, circuit complexity and operating speed increase. Additionally, ring oscillator type voltage-controlled oscillators have a narrow frequency range and may not be able to cover the frequency target in high-volume production applications due to process, voltage and/or temperature variations. A low power and low jitter phase-locked loop to generate a plurality of high speed clocks is desired.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.